As a synchronous memory to/from which data is input/output at a double data rate, a DDR-SDRAM (Synchronous Dynamic Random Access Memory) for example is known. For the purpose of high-speed clock synchronous communication, the DDR-SDRAM outputs a data signal and a strobe signal synchronized with the data signal. The data signal and the strobe signal which are output from the DDR-SDRAM have respective edges that coincide with each other.
In the interface circuit receiving the data signal and the strobe signal which are output from the DDR-SDRAM, a delay circuit is necessary that delays the received strobe signal by a ¼ period. Delay of the input strobe signal by a ¼ period (corresponding to a phase of 90 degrees) enables the data signal to be taken at both the rising edge and the falling edge of the strobe signal.
As a circuit for adjusting the amount of delay of the strobe signal, a circuit disclosed in Japanese Patent Laying-Open No. 2008-311999 (PTD 1) for example is known. This circuit includes a variable delay unit providing a variable amount of delay, a phase comparison unit, and a delay control unit. The phase comparison unit compares the phase of the strobe signal given from an input buffer gate with the phase of a delay signal given from the variable delay unit. Based on the result of comparison by the phase comparison unit, the delay control unit sets the amount of delay of the variable delay unit.
An operation clock of the DDR-SDRAM is supplied as an external clock from the aforementioned interface circuit. Input/output of data to/from the DDR-SDRAM is synchronized with the external clock. Therefore, the DDR-SDRAM is provided with a regeneration circuit for regenerating an internal clock that is correctly synchronized with the external clock. As such a regeneration circuit, a PLL (Phase Lock Loop) circuit (see for example Japanese Patent Laying-Open No. 2000-323969 (PTD 2)), or a DLL (Delay Lock Loop) circuit (see for example Japanese Patent Laying-Open No. 2009-21706 (PTD 3)), or an SMD (Synchronous Mirror Delay) circuit (see for example Japanese Patent Laying-Open No. 2000-311028 (PTD 4)) is used, for example.